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TSMC to adopt High-NA EUV lithography in 2030 for advanced chip nodes

By PulseAugur Editorial · [1 sources] ·

TSMC has announced plans to integrate High-NA EUV lithography into its manufacturing processes starting in 2030. This advanced technology, developed in collaboration with ASML, will enable finer resolutions for chip production, with the A10 or A11 (1/1.1nm-class) nodes being the most likely candidates for its initial adoption. The transition involves significant industry-wide adjustments, including the development of larger 6x12-inch photomasks to overcome current limitations with 6x6-inch masks, which are crucial for producing large AI accelerators. AI

IMPACT This advancement in lithography will enable the production of more powerful and efficient chips, crucial for scaling AI accelerators and complex transistor architectures.

RANK_REASON Announcement of a major manufacturing technology adoption by a leading semiconductor foundry. [lever_c_demoted from significant: ic=1 ai=0.7]

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AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

TSMC to adopt High-NA EUV lithography in 2030 for advanced chip nodes

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Announcement of a major manufacturing technology adoption by a leading semiconductor foundry. [lever_c_demoted from significant: ic=1 ai=0.7]
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COVERAGE [1]

  1. Tom's Hardware TIER_1 English(EN) · Anton Shilov ·

    TSMC to start using High-NA EUV lithography in 2030 — A10 or A11 technology prime candidates for use

    TSMC discloses plans to use High-NA EUV lithography in 2030, 6×12-inch photomasks with new scanners in 2033.

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