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Researcher creates 'hall of shame' for slowest x86 CPU instructions

A hardware researcher named Christopher Domas has initiated a project to identify the slowest single x86 instruction, creating a leaderboard to rank these performance bottlenecks. The current top offender is the `fxrstor64` instruction, which took an astonishing 198 billion cycles, or 62 seconds, to execute by restoring a 512-byte SIMD register state from memory. Domas achieved this by manipulating memory-mapped I/O and overwhelming the CPU's PCIe fabric to deliberately slow down the instruction's execution. Future leaderboards are planned for ARM and RISC-V architectures, with specific rules ensuring only single instruction latency is measured. AI

IMPACT Provides insights into CPU architecture and instruction-level performance, potentially informing future hardware and software optimizations.

RANK_REASON This is a research project focused on understanding CPU instruction performance by deliberately slowing them down. [lever_c_demoted from research: ic=1 ai=0.4]

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Researcher creates 'hall of shame' for slowest x86 CPU instructions

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This is a research project focused on understanding CPU instruction performance by deliberately slowing them down. [lever_c_demoted from research: ic=1 ai=0.4]
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COVERAGE [1]

  1. Tom's Hardware TIER_1 English(EN) · Jake Roach ·

    Hardware researcher spins up 'CPU deoptimization' project to find the slowest single x86 instruction, creates hall of shame — worst offender takes 198 billion cycles spanning 62 seconds to execute

    One hardware researcher, Christopher Domas (@xoreaxeaxeax on GitHub), is taking a different approach with the CPU Deoptimization leaderboard, which looks not to make Assembly instructions run as fast as possible, but as slow as possible to find the single instruction with the hig…