Researchers have developed a novel two-phase workflow to address the challenge of non-compliant RISC-V extensions in CPU designs. This process leverages the RISC-V Unified Database (UDB) as a central source of truth and employs a Large Language Model (LLM) integrated with Model Context Protocol (MCP) tools to facilitate the migration of extensions into compliant opcode spaces. The workflow automates the inspection of instruction encodings, identification of conflicts, and proposal of remappings, followed by the generation and validation of hardware and software artifacts. AI
IMPACT This workflow demonstrates the practical application of LLMs in automating complex hardware and software engineering tasks for ISA architects.
RANK_REASON The item describes a technical workflow and open-source artifacts for RISC-V extension migration, presented as a project snapshot and author preview. [lever_c_demoted from research: ic=1 ai=1.0]
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- Afonso Nogueira de Sousa Oliveira
- AiNekko
- GNU assembler
- Large Language Model (LLM)
- Model Context Protocol (MCP)
- Portugal
- RISC-V
- Synopsys
- Unified Database (UDB)
- Zephyr
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