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Google's Humufish TPU to use Intel EMIB-T over TSMC CoWoS

By PulseAugur Editorial · [4 sources] ·

Google's upcoming TPU, codenamed Humufish, will reportedly utilize Intel's EMIB-T packaging technology instead of the industry-standard TSMC CoWoS. This move is significant as most current AI training accelerators rely on TSMC's CoWoS. Intel's EMIB-T offers advantages in scalability and cost by embedding small silicon bridges directly into the substrate, avoiding the reticle limits and waste associated with TSMC's large interposers. AI

IMPACT Signals a potential shift in AI hardware packaging, offering scalability and cost benefits that could influence future AI accelerator designs.

RANK_REASON Significant shift in AI accelerator packaging away from industry standard.

Read on X — SemiAnalysis →

AI-generated summary · Google Gemini · from 4 sources. How we write summaries →

Google's Humufish TPU to use Intel EMIB-T over TSMC CoWoS

COVERAGE [4]

  1. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    The risk. Plain EMIB has shipped in volume for years, but EMIB-T is new, and a power-delivering bridge is harder to manufacture at scale. The upside only lands

    The risk. Plain EMIB has shipped in volume for years, but EMIB-T is new, and a power-delivering bridge is harder to manufacture at scale. The upside only lands if Intel can ramp yield and volume on schedule. If it slips, the fallback is the same capacity-constrained CoWoS this

  2. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    Humufish is using EMIB-T. The "T" is TSV. Plain EMIB has no vias in the bridge, so power has to detour around it through the substrate, which strains power deli

    Humufish is using EMIB-T. The "T" is TSV. Plain EMIB has no vias in the bridge, so power has to detour around it through the substrate, which strains power delivery. EMIB-T sends power vertically straight through the bridge, with added capacitors and a ground plane for cleaner

  3. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    So why EMIB?

    So why EMIB? 🟠 EMIB isn't bound by the interposer reticle limit. A CoWoS silicon interposer is printed by lithography, so it is capped by the reticle limit; the monolithic version (CoWoS-S) maxed near 3.3x, which is why TSMC moved to CoWoS-L. EMIB is not bound by the reticle htt…

  4. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    Google's next TPU, codenamed Humufish, is set to use Intel's EMIB-T instead of TSMC CoWoS.

    Google's next TPU, codenamed Humufish, is set to use Intel's EMIB-T instead of TSMC CoWoS. Nearly every leading AI training accelerator today is packaged on a TSMC 2.5D flow, and almost all of it is CoWoS. CoWoS is the industry default, which is exactly why a flagship part https…

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