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FPGA accelerator boosts U-Net energy efficiency with merged arithmetic · 3 sources tracked

By PulseAugur Editorial · [3 sources] ·

Researchers have developed an energy-efficient hardware accelerator for U-Net's convolutional layers, implemented on a field-programmable gate array (FPGA). The proposed merged multiply-add (MMA) architecture fuses operations to reduce latency and improve throughput compared to traditional digit-serial methods. This FPGA-based solution offers significantly higher energy efficiency, achieving up to an order of magnitude improvement over CPU-based inference and a substantial reduction in energy consumption compared to existing MSDF FPGA implementations. AI

IMPACT This research could lead to more energy-efficient AI inference on edge devices, particularly for image segmentation tasks.

RANK_REASON The cluster contains academic papers detailing a new hardware architecture for accelerating CNNs on FPGAs.

Read on Hugging Face Daily Papers →

AI-generated summary · Google Gemini · from 3 sources. How we write summaries →

FPGA accelerator boosts U-Net energy efficiency with merged arithmetic · 3 sources tracked

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Research
The cluster contains academic papers detailing a new hardware architecture for accelerating CNNs on FPGAs.
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3 independent sources
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83 days old
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COVERAGE [3]

  1. Hugging Face Daily Papers TIER_1 English(EN) ·

    Energy-Efficient CNN Acceleration with MSDF Digit-Serial Arithmetic on FPGA

    This paper presents an energy-efficient hardware acceleration of the convolutional layers in the U-Net architecture for image segmentation, implemented on FPGA. While digit-serial arithmetic, particularly most-significant-digit-first (MSDF) techniques, offers a compact hardware f…

  2. arXiv cs.CV TIER_1 English(EN) · Muhammad Usman, Yousef Sadegheih, Dorit Merhof ·

    Energy-Efficient CNN Acceleration with MSDF Digit-Serial Arithmetic on FPGA

    arXiv:2606.25562v1 Announce Type: cross Abstract: This paper presents an energy-efficient hardware acceleration of the convolutional layers in the U-Net architecture for image segmentation, implemented on FPGA. While digit-serial arithmetic, particularly most-significant-digit-fi…

  3. arXiv cs.CV TIER_1 English(EN) · Dorit Merhof ·

    Energy-Efficient CNN Acceleration with MSDF Digit-Serial Arithmetic on FPGA

    This paper presents an energy-efficient hardware acceleration of the convolutional layers in the U-Net architecture for image segmentation, implemented on FPGA. While digit-serial arithmetic, particularly most-significant-digit-first (MSDF) techniques, offers a compact hardware f…

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