New framework enhances PLC formal verification with broader language support

Researchers have developed ESBMC-PLC+, a new framework for formally verifying Programmable Logic Controller (PLC) programs. This successor to PLCverif addresses limitations by supporting Ladder Diagram (LD) and Structured Text (ST) programming languages, along with graphical PLCopen XML. ESBMC-PLC+ utilizes the ESBMC backend for unbounded safety proofs and demonstrates significant speed improvements over existing tools like nuXmv on timer-intensive programs. AI

IMPACT Enhances the reliability and safety of industrial control systems by improving formal verification capabilities for PLC programs.

RANK_REASON The cluster describes a new academic paper detailing a novel framework for formal verification of PLC programs. [lever_c_demoted from research: ic=1 ai=0.4]

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• CERN
• ESBMC-GraphPLC
• ESBMC-PLC+
• IEC 61131-3
• MATIEC
• nuXmv
• PLCverif

• paper
• other

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