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New framework enhances PLC formal verification with broader language support

By PulseAugur Editorial · [1 sources] ·

Researchers have developed ESBMC-PLC+, a new framework for formally verifying Programmable Logic Controller (PLC) programs. This successor to PLCverif addresses limitations by supporting Ladder Diagram (LD) and Structured Text (ST) programming languages, along with graphical PLCopen XML. ESBMC-PLC+ utilizes the ESBMC backend for unbounded safety proofs and demonstrates significant speed improvements over existing tools like nuXmv on timer-intensive programs. AI

IMPACT Enhances the reliability and safety of industrial control systems by improving formal verification capabilities for PLC programs.

RANK_REASON The cluster describes a new academic paper detailing a novel framework for formal verification of PLC programs. [lever_c_demoted from research: ic=1 ai=0.4]

Read on arXiv cs.CL →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

New framework enhances PLC formal verification with broader language support

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The cluster describes a new academic paper detailing a novel framework for formal verification of PLC programs. [lever_c_demoted from research: ic=1 ai=0.4]
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COVERAGE [1]

  1. arXiv cs.CL TIER_1 English(EN) · Pierre Dantas, Lucas Cordeiro, Waldir Junior ·

    ESBMC-PLC+: A Unified IEC~61131-3 Formal Verification Framework as a PLCverif Successor

    arXiv:2606.23870v1 Announce Type: cross Abstract: PLCverif is the most mature open-source platform for PLC formal verification, developed at CERN and in production use since 2019. Yet it has two fundamental limitations: no support for Ladder Diagram (LD) programs, the dominant PL…

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