HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
Researchers have developed HAVEN, a novel system designed to improve the generation of Universal Verification Methodology (UVM) testbenches using Large Language Models (LLMs). HAVEN addresses the challenge of LLMs producing incorrect Hardware Description Language (HDL) code by employing a hybrid approach that avoids direct HDL generation. Instead, it uses LLM agents to create architectural plans and a template engine with a specialized Domain-Specific Language (DSL) to construct UVM components and sequences. AI
IMPACT Enhances LLM capabilities for hardware verification, potentially reducing IC development cycles.
