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HAVEN system uses LLMs to automate IC testbench generation with high coverage

By PulseAugur Editorial · Summary by gemini-2.5-flash-lite from 2 sources

Researchers have developed HAVEN, a novel system designed to improve the generation of Universal Verification Methodology (UVM) testbenches using Large Language Models (LLMs). HAVEN addresses the challenge of LLMs producing incorrect Hardware Description Language (HDL) code by employing a hybrid approach that avoids direct HDL generation. Instead, it uses LLM agents to create architectural plans and a template engine with a specialized Domain-Specific Language (DSL) to construct UVM components and sequences. AI

Summary written by gemini-2.5-flash-lite from 2 sources. How we write summaries →

IMPACT Enhances LLM capabilities for hardware verification, potentially reducing IC development cycles.

RANK_REASON Academic paper detailing a new system for LLM-assisted testbench generation.

Read on arXiv cs.AI →

COVERAGE [2]

  1. arXiv cs.AI TIER_1 · Chang-Chih Meng, Yu-Ren Lu, Guan-Yu Lin, Tsung Tai Yeh, Kai-Chiang Wu, I-Chen Wu ·

    HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs

    arXiv:2604.27643v1 Announce Type: cross Abstract: Integrated Circuit (IC) verification consumes nearly 70% of the IC development cycle, and recent research leverages Large Language Models (LLMs) to automatically generate testbenches and reduce verification overhead. However, LLMs…

  2. Hugging Face Daily Papers TIER_1 ·

    HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs

    Integrated Circuit (IC) verification consumes nearly 70% of the IC development cycle, and recent research leverages Large Language Models (LLMs) to automatically generate testbenches and reduce verification overhead. However, LLMs have difficulty generating testbenches correctly.…

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