AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting
Researchers have developed AUTOGATE, a novel framework for optimizing RTL (Register-Transfer Level) designs to reduce dynamic power consumption through automated clock gating. This system utilizes a co-design approach combining machine learning and large language models (LLMs) to analyze waveform data and rewrite RTL code. AUTOGATE addresses limitations of previous LLM-based methods by processing distilled waveform representations and employing a hierarchical multi-agent architecture for scalability across large codebases. AI
IMPACT This research introduces a novel LLM-based framework for optimizing hardware designs, potentially improving efficiency in chip development.