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AUTOGATE uses LLMs for automated RTL power optimization

Researchers have developed AUTOGATE, a novel framework for optimizing RTL (Register-Transfer Level) designs to reduce dynamic power consumption through automated clock gating. This system utilizes a co-design approach combining machine learning and large language models (LLMs) to analyze waveform data and rewrite RTL code. AUTOGATE addresses limitations of previous LLM-based methods by processing distilled waveform representations and employing a hierarchical multi-agent architecture for scalability across large codebases. AI

IMPACT This research introduces a novel LLM-based framework for optimizing hardware designs, potentially improving efficiency in chip development.

RANK_REASON The cluster describes a research paper detailing a new method for RTL power optimization using LLMs. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.AI →

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COVERAGE [1]

  1. arXiv cs.AI TIER_1 English(EN) · Yiting Wang, Chenhui Deng, Chia-Tung Ho, Yanqing Zhang, Zhuo Feng, Cunxi Yu, Ang Li, Gang Qu, Brucek Khailany ·

    AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting

    arXiv:2606.17461v1 Announce Type: cross Abstract: Fine-grain clock gating (FGCG) is among the most effective techniques for reducing dynamic power, yet current FGCG optimization flows remain largely manual. Recent LLM-based RTL optimization approaches remain limited by two key dr…