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AI model FusionCell predicts circuit performance using layout and topology

Researchers have developed FusionCell, a novel AI model designed to predict the performance of standard cells in digital circuits. This model uniquely integrates both layout geometry and netlist topology, overcoming limitations of previous predictors that often ignored physical layout. FusionCell utilizes a dual-modality approach with a DeiT encoder for layouts and a graph transformer for netlists, fusing them via a topology-guided mechanism. Experiments on a 7nm dataset show FusionCell significantly reduces regression error, achieving an average MAPE of 0.92 percent, and accelerates characterization by orders of magnitude compared to traditional circuit simulation. AI

Summary written by gemini-2.5-flash-lite from 1 source. How we write summaries →

IMPACT Accelerates chip design by orders of magnitude, enabling faster iteration and optimization of digital circuits.

RANK_REASON The cluster contains an academic paper detailing a new AI model for a specific technical problem. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.AI →

COVERAGE [1]

  1. arXiv cs.AI TIER_1 · Haoyi Zhang, Kairong Guo, Bojie Zhang, Yibo Lin, Runsheng Wang ·

    FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction

    arXiv:2605.20287v1 Announce Type: cross Abstract: Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization still relies on slow simulation sweeps, and many fast predictors ignore layout…