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TSMC explores in-memory compute and 3D DRAM for AI needs

TSMC is developing a new in-memory compute technology that integrates memory directly into advanced logic chips. This approach, presented at the 2025 VLSI Symposium, uses a 1T1C cell built into the chip's interconnect layers to create a low-power, low-latency cache. The technology demonstrated fast read/write speeds and high endurance, positioning it as a denser alternative to SRAM for processor caches. Additionally, TSMC is reportedly considering manufacturing 3D DRAM at NVIDIA's request to address AI-driven memory shortages, which would place them in direct competition with existing DRAM manufacturers. AI

IMPACT This development could alleviate AI memory shortages and improve AI model performance through faster, more integrated compute and memory.

RANK_REASON TSMC is exploring new memory technologies and potential manufacturing of 3D DRAM, which are significant moves in the semiconductor industry driven by AI demand. [lever_c_demoted from significant: ic=1 ai=0.7]

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AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

TSMC explores in-memory compute and 3D DRAM for AI needs

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3 / 100
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TSMC is exploring new memory technologies and potential manufacturing of 3D DRAM, which are significant moves in the semiconductor industry driven by AI demand. [lever_c_demoted from significant: i…
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infra, product
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High
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Breaking (< 6h)
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COVERAGE [1]

  1. r/LocalLLaMA TIER_1 English(EN) · /u/Terminator857 ·

    TSMC might do in memory compute for us

    <!-- SC_OFF --><div class="md"><p>At the 2025 VLSI Symposium, TSMC presented a memory technology based on oxide semiconductors, using a cell made of one transistor and one capacitor (1T1C). The goal was to integrate this memory into advanced logic chips and give processors a cach…