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New framework optimizes optical flow networks for microcontrollers

By PulseAugur Editorial · [1 sources] ·

Researchers have developed PACE-NAS, a novel neural architecture search framework designed to optimize optical flow networks for microcontrollers with neural accelerators. This framework decouples memory constraints from latency by first fixing the backbone and its peak SRAM usage, then searching for optimal operators and depths. When applied to the EdgeFlowNet model on a Grove Vision AI V2 board featuring an Ethos-U55 accelerator, the optimized MCUFlowNet variants demonstrated improved performance, with MCUFlowNet-S running 1.76x faster than the original EdgeFlowNet at a slightly higher error rate. The framework also showed promise for semantic segmentation tasks, with a searched PIDNet-S variant achieving faster speeds with comparable accuracy. AI

IMPACT Enables more efficient AI processing on resource-constrained edge devices like microcontrollers.

RANK_REASON Research paper detailing a new neural architecture search framework for microcontrollers. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.CV →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

New framework optimizes optical flow networks for microcontrollers

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Research paper detailing a new neural architecture search framework for microcontrollers. [lever_c_demoted from research: ic=1 ai=1.0]
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COVERAGE [1]

  1. arXiv cs.CV TIER_1 English(EN) · Enmin Lin, Jona Beysens ·

    MCUFlowNet: Hardware-Aware Neural Architecture Search for Optical Flow on Microcontrollers

    arXiv:2611.08147v1 Announce Type: new Abstract: Dense optical flow allows small drones to avoid obstacles. However, few dense optical flow networks are designed for microcontrollers (MCUs) with neural accelerators, whose on-chip SRAM limits the input resolution. We present PACE-N…

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