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Tohoku University and Aisin embed STT-MRAM for faster AI edge inference

Researchers from Tohoku University, in collaboration with automotive supplier Aisin, have developed a new method for AI edge inference by embedding 32MB of STT-MRAM directly onto a 16nm TSMC chip. This integration eliminates the need for external DRAM, resulting in significantly reduced inference times of 58.5ms and boot times of 65.7ms. The innovation also boasts an energy efficiency of 50.7mJ/frame, demonstrating the production readiness of non-volatile memory for advanced driver-assistance systems (ADAS). AI

IMPACT This development could lead to more efficient and faster AI processing at the edge, impacting the performance and capabilities of devices like autonomous vehicles.

RANK_REASON Research paper detailing a new technological approach for AI hardware. [lever_c_demoted from research: ic=1 ai=0.7]

Read on Mastodon — mastodon.social →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

Tohoku University and Aisin embed STT-MRAM for faster AI edge inference

How we ranked this

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14 / 100
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Tool
Research paper detailing a new technological approach for AI hardware. [lever_c_demoted from research: ic=1 ai=0.7]
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Only one publisher covered this so far. Single-source stories can still rank when the publisher is high-authority, but they lack cross-source corroboration.
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infra, product
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High
Clearly on-topic for AI-industry coverage.
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Breaking (< 6h)
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COVERAGE [1]

  1. Mastodon — mastodon.social TIER_1 English(EN) · asiaai ·

    Ditching external DRAM cuts AI edge inference to 58.5ms and slashes boot time to 65.7ms. Tohoku University and automotive tier-one Aisin achieved this by embedd

    Ditching external DRAM cuts AI edge inference to 58.5ms and slashes boot time to 65.7ms. Tohoku University and automotive tier-one Aisin achieved this by embedding 32MB of STT-MRAM onto a 16nm TSMC chip, delivering 50.7mJ/frame efficiency. It's solid proof that non-volatile memor…