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New benchmark tests LLMs on analog circuit porting, revealing limitations

Researchers have introduced AnalogPortBench, a new benchmark designed to evaluate Large Language Models (LLMs) on the task of porting analog circuits across different process nodes. The benchmark includes 54 tasks involving ten circuits, ranging from simple current mirrors to complex telescopic amplifiers, and tests their transferability from a 0.18 $\mu$m process to the SKY130 PDK. Initial evaluations of six frontier LLMs revealed that while models can port basic circuits, they struggle with headroom-sensitive designs and rarely identify infeasible specifications, with simulation feedback proving more beneficial than increased sample size or advanced reasoning. AI

IMPACT This benchmark could guide the development of LLMs capable of more sophisticated analog circuit design and porting, potentially accelerating hardware development.

RANK_REASON The cluster contains an academic paper introducing a new benchmark for evaluating LLMs on a specific technical task. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.AI →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

New benchmark tests LLMs on analog circuit porting, revealing limitations

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The cluster contains an academic paper introducing a new benchmark for evaluating LLMs on a specific technical task. [lever_c_demoted from research: ic=1 ai=1.0]
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COVERAGE [1]

  1. arXiv cs.AI TIER_1 English(EN) · Saeid Rajabi, Aly Moussa, Vishal Saxena, Chengmo Yang, Satwik Patnaik ·

    AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting

    arXiv:2610.33088v1 Announce Type: cross Abstract: Analog circuit design still relies heavily on expert knowledge, and porting proven designs to new process nodes is a recurring bottleneck. As a lower supply reduces available voltage headroom, a working topology may require redesi…