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Graph Neural Network Enhances Lithography Layout Decomposition

By PulseAugur Editorial · [1 sources] ·

Researchers have developed a novel method for layout decomposition in directed self-assembly integrated with multiple patterning lithography (DSA-MP). This new approach utilizes a graph neural network to guide local refinement, addressing limitations in existing methods that struggle with solution quality, runtime, and critical edge-to-edge spacing constraints of DSA templates. The proposed technique aims to improve manufacturability and has demonstrated superior solution quality and faster convergence compared to current state-of-the-art methods across various scales and design parameters. AI

IMPACT This research could lead to more efficient and cost-effective semiconductor manufacturing processes by improving layout decomposition for advanced lithography techniques.

RANK_REASON The cluster contains a research paper detailing a new method for a technical problem in semiconductor manufacturing. [lever_c_demoted from research: ic=1 ai=0.7]

Read on arXiv cs.AI →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

Graph Neural Network Enhances Lithography Layout Decomposition

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The cluster contains a research paper detailing a new method for a technical problem in semiconductor manufacturing. [lever_c_demoted from research: ic=1 ai=0.7]
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COVERAGE [1]

  1. arXiv cs.AI TIER_1 English(EN) · Yu Feng, Liyi Zhou, Haoyu Wang, Yiming Xu, Hao Geng, Shaozhi Deng, Ningsheng Xu, Shisheng Xiong ·

    GNN-Guided Local Refinement for Efficient Layout Decomposition with DSA-MP

    arXiv:2610.22214v1 Announce Type: new Abstract: Multiple patterning lithography (MPL) has been widely used to improve lithography resolution in advanced nodes, but it faces cost limits as feature sizes shrink. Directed self-assembly (DSA) offers a cost-effective complement, exten…

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