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New benchmark tests AI's ability to design complex transistor layouts

By PulseAugur Editorial · [1 sources] ·

A new benchmark called 2D-FET-Bench V2 has been developed to evaluate the ability of language models to design field-effect transistor (FET) layouts. This benchmark consists of 128 tasks, each providing textual specifications and contour coordinates derived from microscopy images of two-dimensional flakes. The system generates layouts in GDSII format, which are then verified for geometric and structural correctness. In evaluations, GPT5.6-Luna with the ReAct-3 workflow achieved a 62.3% success rate on tasks, solving 80.5% of tasks at least once and demonstrating consistency in 43.8% of attempts. AI

IMPACT This benchmark could accelerate AI-driven design in semiconductor manufacturing and materials science.

RANK_REASON The item describes a new benchmark and evaluation of AI models for a specific scientific/engineering task, published on arXiv. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.AI →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

New benchmark tests AI's ability to design complex transistor layouts

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The item describes a new benchmark and evaluation of AI models for a specific scientific/engineering task, published on arXiv. [lever_c_demoted from research: ic=1 ai=1.0]
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COVERAGE [1]

  1. arXiv cs.AI TIER_1 English(EN) · Dunzhi Zhou, Chengyu Zhu, Gang Qiu, Caiwen Ding ·

    2d-fet-bench: from spatial reasoning to fet design on flakes

    arXiv:2610.07423v1 Announce Type: new Abstract: Field-effect transistor (FET) layouts on exfoliated two-dimensional flakes are typically drawn by hand for each flake, placing contacts and gates to match its position and outline in optical micrographs. To our knowledge, no executa…

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