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New framework LevelSyn uses GNNs for physical-aware logic synthesis

By PulseAugur Editorial · [1 sources] ·

Researchers have developed LevelSyn, a new framework that integrates logic synthesis with physical design for integrated circuits. It uses a level-asynchronous Graph Neural Network (GNN) to predict gate coordinates and capture structural semantics of And-Inverter Graphs (AIGs). This approach aims to reduce power consumption, improve performance, and accelerate design closure by providing more accurate spatial estimations than traditional methods. Experiments show significant improvements in power reduction, timing delay, and a drastic decrease in design rule check violations. AI

IMPACT This research could accelerate integrated circuit design cycles and improve power efficiency by integrating AI-driven spatial estimation into the synthesis process.

RANK_REASON This is a research paper detailing a new method for logic synthesis in integrated circuit design. [lever_c_demoted from research: ic=1 ai=0.7]

Read on arXiv cs.AI →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

New framework LevelSyn uses GNNs for physical-aware logic synthesis

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This is a research paper detailing a new method for logic synthesis in integrated circuit design. [lever_c_demoted from research: ic=1 ai=0.7]
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COVERAGE [1]

  1. arXiv cs.AI TIER_1 English(EN) · Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu ·

    LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

    arXiv:2609.03594v1 Announce Type: cross Abstract: As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design c…

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