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LevelSyn uses GNNs for physical-aware logic synthesis, improving IC design

By PulseAugur Editorial · [2 sources] ·

Researchers have developed LevelSyn, a new framework for physical-aware logic synthesis that uses a level-asynchronous graph neural network (GNN) to improve the integration of logic and physical design in integrated circuits. This approach captures structural and directional semantics of And-Inverter Graphs (AIGs) to predict gate coordinates with high fidelity. LevelSyn integrates these spatial insights into the Berkeley ABC framework, demonstrating significant improvements in power reduction, timing delay, and a drastic decrease in design rule check violations. AI

IMPACT This framework could accelerate integrated circuit design cycles by improving the accuracy of physical estimations in logic synthesis.

RANK_REASON The cluster describes a new research paper detailing a novel framework for logic synthesis using graph neural networks.

Read on Hugging Face Daily Papers →

AI-generated summary · Google Gemini · from 2 sources. How we write summaries →

LevelSyn uses GNNs for physical-aware logic synthesis, improving IC design

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The cluster describes a new research paper detailing a novel framework for logic synthesis using graph neural networks.
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COVERAGE [2]

  1. arXiv cs.AI TIER_1 English(EN) · Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu ·

    LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

    arXiv:2609.03594v1 Announce Type: cross Abstract: As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design c…

  2. Hugging Face Daily Papers TIER_1 English(EN) ·

    LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

    As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design closure cycles. Traditional logic synthesis relies …

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