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Fujitsu unveils Monaka AI CPU with stacked cache design

By PulseAugur Editorial · [1 sources] ·

Fujitsu has unveiled its new Monaka server CPU, designed for AI performance and power efficiency in green data centers. The chip features a unique three-die stack: a 2nm core die, a 5nm die for the entire last-level cache, and a 5nm I/O die. This design, which separates the cache onto its own die, differs from existing technologies like AMD's 3D V-Cache. The Monaka CPU will be available in 350W and 500W configurations, with volume production slated for 2027. AI

IMPACT This new CPU architecture with stacked cache and AI-specific optimizations could improve data center efficiency and performance for AI workloads.

RANK_REASON New CPU architecture and design from a major hardware vendor. [lever_c_demoted from significant: ic=1 ai=0.7]

Read on Tom's Hardware →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

Fujitsu unveils Monaka AI CPU with stacked cache design

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Signal score
31 / 100
Composite score across the factors below. Higher = stronger signal that this story matters right now.
Newsworthiness bucket
Research
New CPU architecture and design from a major hardware vendor. [lever_c_demoted from significant: ic=1 ai=0.7]
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Single-source cluster
Only one publisher covered this so far. Single-source stories can still rank when the publisher is high-authority, but they lack cross-source corroboration.
Topics
model release, infra
Editorial topic classification. Feeds into how the story surfaces on /topic/<slug> hub pages and into the per-entity coverage mix.
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High
Clearly on-topic for AI-industry coverage.
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Breaking (< 6h)
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Full methodology in our editorial standards.

COVERAGE [1]

  1. Tom's Hardware TIER_1 English(EN) · Luke James ·

    Hot Chips 2026: Fujitsu's Monaka CPU stacks its entire cache on a separate 5nm die and narrows to 256-bit SVE2 — 350W and 500W SKUs due in 2027

    Fujitsu gave us a detailed look at its 144-core Monaka server CPU at Hot Chips 2026 on August 24, confirming for the first time that the Arm chip runs dual 256-bit SVE2 vector units, down from the 512-bit SVE in its A64FX predecessor.

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