NeuroAbs framework uses LLMs to accelerate hardware property checking

Researchers have developed NeuroAbs, a novel neuro-symbolic framework designed to accelerate hardware property checking through RTL abstraction. This framework leverages Large Language Models (LLMs) to identify signals for abstraction and combines LLM-based abstraction with an AST-based symbolic representation. The soundness of each abstraction is verified using satisfiability modulo theories (SMT) solving, with counterexample-guided abstraction refinement (CEGAR) employed for iterative model improvement. Experimental results indicate that NeuroAbs significantly enhances the efficiency of hardware property checking. AI

IMPACT This framework could improve the efficiency and reduce the cost of verifying complex hardware designs.

RANK_REASON The cluster describes a new research paper detailing a novel framework for hardware verification. [lever_c_demoted from research: ic=1 ai=1.0]

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• arXiv
• NeuroAbs
• satisfiability modulo theories

• paper
• infra

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