New AI framework tackles semiconductor design rule violations

Researchers have developed SCALE, a novel framework designed to address complex design rule violations in semiconductor manufacturing at advanced sub-2nm nodes. The system utilizes a self-supervised layout-generation stage where a fine-tuned language model learns to reconstruct masked polygons from their surrounding context. This approach enables the model to generate DRC-annotated layout-violation pairs, which are then used to fine-tune a domain-adapted vision-language model (VLM). This VLM provides rule-aware geometric guidance for local DRV repair, significantly improving the solve rates of state-of-the-art agents by up to 25% on real-world cases. AI

IMPACT This framework could accelerate the design process for advanced semiconductors by automating the detection and repair of complex layout violations.

RANK_REASON The cluster describes a research paper detailing a new technical framework for a specific engineering problem. [lever_c_demoted from research: ic=1 ai=1.0]

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• Large Language Models
• SCALE
• vision-language model

• paper
• infra

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