Researchers have developed a new methodology for screening chiplet-based AI systems-on-chip (SoCs) to ensure post-assembly reliability, moving beyond traditional Known Good Die (KGD) methods. This new approach, termed Known Good Reliable Die (KGRD), formalizes the screening process as a constrained inference problem. It introduces a Bayesian probabilistic risk model to predict post-assembly failure likelihood based on pre-assembly data, along with a safety-gated decision architecture that guarantees a specific post-assembly failure probability. The system also incorporates uncertainty-aware disposition boundaries and a feedback mechanism for continuous model improvement without compromising reliability constraints. AI
IMPACT Enhances the reliability of AI hardware by improving chip screening processes.
RANK_REASON Academic paper detailing a new methodology for semiconductor testing. [lever_c_demoted from research: ic=1 ai=0.7]
Read on Hugging Face Daily Papers →
- AI systems-on-chip
- Bayesian probabilistic risk model
- Bayes-optimal decision theory
- Hugging Face
- Known Good Die
- Known Good Reliable Die
- Monte Carlo method
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