Graph Neural Networks Learn Structural Manipulability in Hardware Designs

Researchers have developed a method to quantify the structural manipulability of gate-level netlists, which are foundational to hardware design. This score characterizes node-level flexibility by analyzing path participation, k-core embedding, symmetry, and centrality within the netlist's graph structure. Graph neural networks were employed to learn this score, with experiments on ISCAS85 and EPFL benchmarks showing that hierarchical models provide the most consistent rankings. The approach also demonstrated its utility in identifying distinct structural patterns in Trojan-injected circuits, offering a complementary perspective to functional analysis. AI

IMPACT This research offers a new method for analyzing hardware security and design by applying graph neural networks to structural properties of netlists.

RANK_REASON Academic paper detailing a novel methodology for analyzing hardware netlists using graph neural networks. [lever_c_demoted from research: ic=1 ai=1.0]

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