SemiAnalysis criticizes AMD leadership for hindering vLLM progress

By PulseAugur Editorial · [7 sources] · 2026-07-20 20:19

SemiAnalysis has criticized AMD's leadership for diverting computing resources from its internal vLLM team, which has led to a regression in the development of automated testing for vLLM. This diversion of clusters is hindering AMD's progress in achieving parity with CUDA's vLLM testing capabilities. Despite these challenges, AMD's DI CI system, implemented after initial requests and meetings, has successfully identified significant bugs in models like DeepSeek V4 and Kimi, improving overall code quality. AI

IMPACT AMD's internal resource allocation decisions may slow its progress in developing competitive AI models and testing infrastructure.

RANK_REASON The cluster consists of critical tweets from SemiAnalysis regarding AMD's internal resource allocation and its impact on AI development, rather than an official announcement or release from AMD.

Read on X — SemiAnalysis →

AI-generated summary · Google Gemini · from 7 sources. How we write summaries →

SemiAnalysis criticizes AMD leadership for hindering vLLM progress

COVERAGE [7]

X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-07-20 20:19

@sgl_project @AnushElangovan @LisaSu We hope AMD leadership can reprioritize providing its internal vLLM team with stable clusters so that AMD’s hardcore intern

@sgl_project @AnushElangovan @LisaSu We hope AMD leadership can reprioritize providing its internal vLLM team with stable clusters so that AMD’s hardcore internal vLLM engineers can do the work required to reach 90%+ gating parity with CUDA vLLM. 7/7🧵
X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-07-20 20:19

@sgl_project @AnushElangovan @LisaSu Gating/blocking tests mean that the tests are of the highest quality, since PRs cannot merge unless the tests pass. While A

@sgl_project @AnushElangovan @LisaSu Gating/blocking tests mean that the tests are of the highest quality, since PRs cannot merge unless the tests pass. While AMD leadership may distract non-technical folks by showing its non-gating pass rate, gating parity and the gating pass ra…
X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-07-20 20:19

@sgl_project @AnushElangovan @LisaSu On the vLLM side, progress on automated vLLM gating tests has massively regressed due to AMD cluster infrastructure stabili

@sgl_project @AnushElangovan @LisaSu On the vLLM side, progress on automated vLLM gating tests has massively regressed due to AMD cluster infrastructure stability issues. AMD’s hardcore engineers had been making good progress on vLLM gating over the past couple of weeks until AMD…
X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-07-20 20:19

@sgl_project @AnushElangovan @LisaSu In order for AMD DI CI to reach parity with CUDA SGLang, it also needs to implement nightly tests for the WideEP decode opt

@sgl_project @AnushElangovan @LisaSu In order for AMD DI CI to reach parity with CUDA SGLang, it also needs to implement nightly tests for the WideEP decode optimization, on which it is making good progress in 31500. 4/7🧵
X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-07-20 20:19

@sgl_project @AnushElangovan @LisaSu The first bug it caught was an AMD MoRI buffer MR error in #30336 on DeepSeek V4. The second was a Kimi K2.6 error caused b

@sgl_project @AnushElangovan @LisaSu The first bug it caught was an AMD MoRI buffer MR error in #30336 on DeepSeek V4. The second was a Kimi K2.6 error caused by an AMD AITER kernel regression in #30433 that made Kimi’s math accuracy massively lower. Through AMD’s nightly CI, the…
X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-07-20 20:19

@sgl_project The first AMD DI CI PR, #29084, was implemented three months after SemiAnalysis’s initial request and multiple meetings with @AnushElangovan and Va

@sgl_project The first AMD DI CI PR, #29084, was implemented three months after SemiAnalysis’s initial request and multiple meetings with @AnushElangovan and Vamsi (Head of AI), as well as a meeting with @LisaSu early in the year regarding improvements to code quality. We will wa…
X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-07-20 20:19

Great work by the AMD @sgl_project team on enabling nightly disaggregated serving CI to improve code quality! It has already caught and prevented 2 massive bugs

Great work by the AMD @sgl_project team on enabling nightly disaggregated serving CI to improve code quality! It has already caught and prevented 2 massive bugs from reaching customers, as we explained before 👇️ 1/7🧵 https://t.co/cUCr6niKEt

COVERAGE [7]

@sgl_project @AnushElangovan @LisaSu We hope AMD leadership can reprioritize providing its internal vLLM team with stable clusters so that AMD’s hardcore intern

@sgl_project @AnushElangovan @LisaSu Gating/blocking tests mean that the tests are of the highest quality, since PRs cannot merge unless the tests pass. While A

@sgl_project @AnushElangovan @LisaSu On the vLLM side, progress on automated vLLM gating tests has massively regressed due to AMD cluster infrastructure stabili

@sgl_project @AnushElangovan @LisaSu In order for AMD DI CI to reach parity with CUDA SGLang, it also needs to implement nightly tests for the WideEP decode opt

@sgl_project @AnushElangovan @LisaSu The first bug it caught was an AMD MoRI buffer MR error in #30336 on DeepSeek V4. The second was a Kimi K2.6 error caused b

@sgl_project The first AMD DI CI PR, #29084, was implemented three months after SemiAnalysis’s initial request and multiple meetings with @AnushElangovan and Va

Great work by the AMD @sgl_project team on enabling nightly disaggregated serving CI to improve code quality! It has already caught and prevented 2 massive bugs

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