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New SMART framework uses ML to accelerate digital circuit reliability analysis

By PulseAugur Editorial · [3 sources] ·

Researchers have developed SMART, a new framework that combines Machine Learning with Monte Carlo simulation to speed up the analysis of transistor aging and process variation in digital circuits. This approach uses Random Forest regression and Bayesian Optimization to predict gate delay distributions, significantly reducing analysis time and maintaining high accuracy. SMART aims to provide a scalable solution for designing more reliable digital systems, addressing the limitations of traditional simulation methods in deep nanometer CMOS technology. AI

IMPACT Accelerates design space exploration for reliable digital systems by reducing analysis time for transistor aging and process variation.

RANK_REASON The cluster describes a novel framework presented in an academic paper for analyzing digital circuit reliability using machine learning techniques.

Read on arXiv cs.LG →

AI-generated summary · Google Gemini · from 3 sources. How we write summaries →

New SMART framework uses ML to accelerate digital circuit reliability analysis

COVERAGE [3]

  1. arXiv cs.LG TIER_1 English(EN) · Arash Esshaghi, Siavash Es'haghi, Gholamreza Shahabadi, Alireza Moradi ·

    SMART: A Machine Learning and Monte Carlo Framework for Rapid Analysis of Stochastic Transistor Aging and Process Variation in Digital Circuits

    arXiv:2607.05187v1 Announce Type: new Abstract: As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV). Traditional reliab…

  2. arXiv cs.LG TIER_1 English(EN) · Alireza Moradi ·

    SMART: A Machine Learning and Monte Carlo Framework for Rapid Analysis of Stochastic Transistor Aging and Process Variation in Digital Circuits

    As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV). Traditional reliability analysis methods, which rely on computatio…

  3. Hugging Face Daily Papers TIER_1 English(EN) ·

    SMART: A Machine Learning and Monte Carlo Framework for Rapid Analysis of Stochastic Transistor Aging and Process Variation in Digital Circuits

    As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV). Traditional reliability analysis methods, which rely on computatio…

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