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Neuromorphic Silicon Suite Unveiled for Edge AI Systems

Researchers have developed a suite of four digital intellectual property (IP) blocks for edge neuromorphic systems, implemented in standard-cell CMOS on the SkyWater 130 nm process. These blocks include a process, voltage, and temperature (PVT) sensor with random number generation capabilities, a stochastic leaky integrate-and-fire (LIF) neuron for probabilistic inference, an on-chip spike-timing-dependent plasticity (STDP) controller for local learning, and a memristive-crossbar controller for interfacing with analogue memory. The suite is designed to be compact and configurable, sharing a common serial peripheral interface (SPI) register file, and has undergone extensive simulation-based verification. AI

IMPACT Enables more compact and configurable edge neuromorphic systems with integrated learning and probabilistic inference capabilities.

RANK_REASON The cluster contains an academic paper detailing the design and development of novel hardware components for neuromorphic systems. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.NE (Neural & Evolutionary) →

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Neuromorphic Silicon Suite Unveiled for Edge AI Systems

COVERAGE [1]

  1. arXiv cs.NE (Neural & Evolutionary) TIER_1 English(EN) · Santhosh Sivasubramani ·

    Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming

    Edge neuromorphic systems need compact, configurable hardware that combines probabilistic inference, local learning, and an interface to emerging analogue memory. We present four interface-compatible digital IP blocks implemented as standard-cell CMOS on the SkyWater 130 nm proce…