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TSMC advances 3D chip stacking roadmap with finer pitches for future CPUs

By PulseAugur Editorial · Summary by gemini-2.5-flash-lite from 1 source

TSMC has revealed its roadmap for System-on-Integrated-Chips (SoIC) 3D stacking technology, aiming to reduce pitch sizes from 6 microns to 4.5 microns by 2029. This advancement will enable face-to-face chiplet stacking, a technology that Fujitsu's upcoming Monaka CPU is expected to leverage. The roadmap indicates TSMC's commitment to pushing the boundaries of semiconductor integration for future high-performance computing. AI

Summary written by gemini-2.5-flash-lite from 1 source. How we write summaries →

IMPACT Advances in chiplet stacking and pitch reduction by TSMC could enable more powerful and efficient AI hardware.

RANK_REASON TSMC's roadmap for advanced 3D stacking technology represents a significant development in semiconductor manufacturing.

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  1. Mastodon — mastodon.social TIER_1 · [email protected] ·

    TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029 — Fujitsu's Monaka CPU to benefit from face-to-face chiplet stacki

    TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029 — Fujitsu's Monaka CPU to benefit from face-to-face chiplet stacking TSMC adds support for face-to-face stacking, 6.5 µm and 4.5 µm pitches for the next generation of SoIC 3D stacking. h…

    LINKS tomshardware.com/tech-industry

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