VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation
Researchers have developed VHDLSuite, a new infrastructure designed to evaluate the performance of Large Language Models (LLMs) in generating VHDL code. This system addresses a gap in current LLM evaluations, which primarily focus on Verilog, by creating a standardized pipeline for VHDL generation, synthesis, and validation. VHDLSuite includes a benchmark with over 200 VHDL problems and a data pipeline that converts Verilog designs into executable VHDL benchmarks, ensuring comprehensive and accurate testing. AI
IMPACT This research provides a framework to better evaluate LLM capabilities in generating VHDL, a crucial hardware description language, potentially improving future hardware design tools.