SwiftCTS: Fast Cross-Design Prediction and Pareto Optimization of Clock Tree Metrics via Few-Shot Calibration
Researchers have developed SwiftCTS, a novel framework for optimizing clock tree synthesis in chip design. This system uses physics-informed surrogate models and gradient-boosted ensembles to achieve rapid predictions and Pareto optimization of power, wirelength, and timing skew metrics. SwiftCTS can adapt to new chip architectures with minimal calibration, significantly reducing prediction errors and enabling the evaluation of thousands of configurations in seconds. AI
IMPACT Accelerates chip design cycles by providing rapid, accurate predictions for clock tree synthesis.