CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation
Researchers have developed a new architecture called CRAM-ER to improve the efficiency and scalability of in-memory computation for deep neural networks. This approach combines spintronic-based Computational Random Access Memory (CRAM) with CMOS adders to mitigate errors inherent in MRAM switching. The system is designed to accelerate matrix-vector multiplications, a key operation in DNNs, by reducing latency and energy consumption compared to traditional CPU/GPU setups. AI
IMPACT This novel architecture could significantly reduce the energy and latency costs of running deep neural networks.